A data processing system typically includes a processing component, memory, and various support circuits, such as conventional cache, power supplies, clock circuits, data registers, input/output interfaces, bus circuitry, and the like to facilitate operation of the system. The processing component may include one or more processors, such as microprocessors. To place a data processing system in a known initial state, the system is typically equipped with a mechanism that causes the processing component to boot or reset (referred to as a “reset condition”). For example, a processor may include a reset pin. As the reset condition is released, the processing component begins to fetch and execute instructions from a memory address known as the processor reset vector (“reset vector”).
The reset vector must point to valid data, such as executable software code. Otherwise, the processing component may execute invalid code, generate an invalid instruction exception, or otherwise enter an undesirable state. The data may include any number of instructions that initialize the system and prepare it for execution of subsequent programming instructions. In some cases, however, the memory resource associated with the reset vector may not be initialized or loaded with the data when the processor exits the reset condition.
For example, it is often desirable to embed a processor within a larger integrated circuit (IC), such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Such an embedded processor is sometimes referred to as an “embedded processor core” or “embedded core.” An embedded processor is typically held in a reset condition unit the host IC is powered and initialized (e.g., initialization of memories, clock circuits, etc. within the IC). Once the IC is initialized, the reset condition is immediately released and the embedded processor begins to fetch and execute instructions mapped to the reset vector.
The data mapped to the reset vector may be stored within internal memory resources of the IC, or within external memory resources accessible by the embedded processor. In some cases, use of the often scarce internal memory resources to store data mapped to the reset vector is undesirable. Moreover, external memory may not be initialized or loaded with data mapped to the reset vector when the embedded processor exits the reset condition, which may result in the embedded processor entering an undesirable state.
Accordingly, there exists a need in the art for a method and apparatus for controlling a processor during initialization of a data processing system.